1. Field of the Invention
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM) using a memory transistor having a charge accumulation layer and a control gate, and to a manufacturing method thereof.
2. Description of the Related Art
A memory cell of an EEPROM having a MOS transistor structure is known which has a charge accumulation layer and a control gate in a gate portion and which uses a tunnel current to inject a charge into the charge accumulation layer and to release a charge from the charge accumulation layer. This memory cell stores, as data “0” and “1”, a difference of threshold voltages resulting from a difference in the charge accumulation state of the charge accumulation layer. For example, in order to inject electrons into a floating gate as the charge accumulation layer, source and drain diffusion layers and a substrate are grounded to apply a positive high voltage to the control gate. At this moment, electrons are injected from the substrate side into the floating gate by the tunnel current. Due to this injection of electrons, the threshold voltage of the memory cell moves in a positive direction. In order to release the electrons in the floating gate, the control gate is grounded to apply a positive high voltage to the source and drain diffusion layers or to the substrate. At this moment, the electrons are released from the floating gate to the substrate side by the tunnel current. Due to this release of electrons, the threshold voltage of the memory cell moves in a negative direction.
However, along with recent marked advancement and digitalization of the information-oriented society, rapid progress is made in the miniaturization and capacity increase of the nonvolatile semiconductor memory device as described above, and product development is gradually becoming more difficult due to problems associated with the miniaturization, such as short channel effect and inter-cell interference effect. The short channel effect is one of the great problems among others, and this causes, for example, deterioration of an on-off ratio, resulting in a significant decrease in the performance as the memory.
In view of such problems, in order to achieve higher density through the miniaturization while suppressing the short channel effect, a cell structure has been proposed wherein a columnar channel provided vertically to a substrate is enclosed by a floating gate and a control gate (refer to JP A 4-79369 (KOKAI).
However, in the cell structure of the above patent document, the control gate and the floating gate are stacked when viewed from the channel in order to increase capacity coupling between the control gate and the floating gate, and in such an array structure, the distance between the cells is desirably about the same as the size of the cell itself to sufficiently increase the density of the cells. However, when employing an actually used size, for example, a cell size and cell pitch of 45 nm or less, it is currently very difficult to create the structure as proposed into such an extremely thin area.
Furthermore, it is essential that a common source and drains for the individual cells be used in the structure in the above patent document. However, when such a structure is employed, there has been a problem that apparent resistance of a cell to be read from changes due to the information (whether “0” or “1”) on other electrically connected cells, and the reading becomes difficult if an actual number (e.g., about several hundred to several thousand) of cells are connected to one word line. In such a case, if the number of cells to be connected to the word line is decreased, the area occupied by, for example, peripheral circuits will be vast, which makes it impossible to increase capacity per unit area.
As described above, to achieve the miniaturization and higher capacity of the EEPROM while effectively suppressing the short channel effect, there are problems such as difficulty in manufacture or difficulty in increasing capacity. Therefore, it has been desired to achieve a semiconductor nonvolatile memory device that is easy to manufacture and capable of increasing capacity while effectively suppressing the short channel effect.